Integrated circuits (ICs) are becoming smaller and more powerful. As ICs become smaller, the location and alignment of features on the ICs becomes more critical. Features, such as transistors and diodes, are created on semiconductor substrates using a process known as photolithography. Photolithography uses optics to define the features on the substrate. A feature may be drawn on a reticle, or mask, and light is shown through the mask so as to project the feature onto a layer of photoresist on the substrate. Photoresist is a light sensitive film that either becomes soluble or insoluble when exposed to light. After the layer of photoresist has been exposed to light, the soluble portion can be removed, typically by immersion in a developer solution. Other processing techniques, such as etching or annealing, may be performed to the underlying substrate that has been exposed as a result of the photolithography.
To form complex features in an IC, several layers of processing need to be completed. For example, to form a metal oxide semiconductor (MOS) transistor, a source and drain may be formed in the substrate using ion implantation. In another region of the substrate, a gate may be formed by depositing films over the entire substrate and removing the unwanted portions of the film. The gate may comprise portions of several film layers.
One reticle or mask may be used to pattern each layer. When more than one reticle is used, the reticles must be aligned properly so that each layer is aligned within a window of tolerance relative to the substrate and the other layers. For example, if the source and drain are created during one process, and the gate during another, and the gate overlies the source, the device will be non-functional. Therefore, proper alignment of the various layers used to construct the device is critical. Typical semiconductor devices now being made require alignments within a tolerance of a few tens of nanometers (nm).
FIG. 1 illustrates typical alignment marks used on conventional reticles. The alignment marks 100 are printed on an edge of the printed field during photolithography. A printed field is a portion of a substrate that typically generates one or more ICs. The alignment marks comprise two boxes 102 and 104, each comprising several bars 102a-d and 104a-d. Each of the bars 102a-d and 104a-d is typically one to two microns wide.
“Overlay” is a term referring to the alignment error between the layers as show in FIG. 1. If the two reticle prints were perfectly aligned, the overlay would be zero, and the centers of the boxes 102 and 104 would overlap perfectly. As shown in FIG. 1, the boxes 102 and 104 are not perfectly aligned and therefore have a non-zero overlay. The overlay is typically measured in two dimensions. The overlay along the x-axis can be determined by measuring the distance between two lines 106 and 108. The line 106 represents the centerline (i.e. average position) of bars 104c and 104d along the x-axis and the line 108 represents the centerline of bars 102c and 102d along the x-axis. Likewise, for the y-axis, the lines 110 and 112 represent the centerlines of bars 104a and 104b, and 102a and 102b, along the y-axis.
The alignment marks 100 are typically inspected using a microscope. The microscope includes a charge coupled device (CCD) to record the image of the alignment marks 100. Conventional CCDs may include an array of pixels that are typically 80-100 nanometers wide. Typical overlay errors that would affect some of these semiconductor processes are on the order of a few tens of nanometers. Due to the fact that the CCD pixel size is much larger than the desired level of accuracy, sub-pixel interpolation is required. Ultimately, the accuracy of this technique is limited by the fact that only a relatively small number of pixels are used to detect the overlay error. This, in combination with quantization effects arising from the large pixel size relative to the overlay error, may introduce errors in the overlay measurement. The impact of measurement error becomes more significant when the size of the pertinent features becomes smaller.